It is known that the majority of data processings relating to pixels, displayed at the conjunctions of predetermined lines and columns, comprise memory means for storing this data, and means for processing stored data. The data relating to a pixel is processed with respect to data relating to each of the pixels situated at least in the immediate vicinity of the pixel in question. Generally speaking, in order to process data relating to a pixel, denoted by a line number and a column number at the conjunction where this pixel is situated, account is taken of the data relating to the pixels situated in a generally square window having at least 9 pixels. This window contains the processed pixel which occupies its center, as well as eight surrounding pixels.
The surrounding pixels are situated at the conjunctions of lines and columns adjacent to the line and column determining the location of the pixel to be processed.
Various devices are known which make it possible to process data relating to each pixel by taking into account the data of the surrounding pixels situated in a predetermined window.
One of these devices uses a "pipeline" structure which splits the processing to be carried out into stages, each stage being operated by a specific module. The different modules may carry out parallel processing, each module operating on the results of the preceding module. This type of device has limited efficiency by splitting the processings into different stages and is ill-suited to different types of processings.
Another device uses an architecture known as systolic network. This architecture may be considered as a generalization of the pipeline structure. In a systolic network, each module may comprise several upstream modules and several downstream modules, but this structure is still more specific than the pipeline structure and more difficult to implement.
Finally, a further device uses structures in the form of processor arrays constituted by elementary processors, disposed in generally rectangular networks. Each elementary processor can be associated with one pixel, or a group of pixels, of the picture and has access to the adjacent pixels by means of links for interconnecting with the adjacent elementary processors within the network.
This is an advantageous structure since it establishes perfect correspondence with the splitting up of the picture into pixels marked by lines or columns. It allows for very high parallelism since all the pixels can be simultaneously processed. However, owing to reasons of integration technology, it presents the drawback of having a number of elementary processors less than the dimensions of the picture which may comprise 128.times.128 pixels or even 512.times.512 pixels. The cost of devices using structures in the form of processor arrays is extremely high. Moreover, it is difficult to implement parallel algorithms in such processor arrays and especially scanning algorithms.